ASML Case Study

M. Hendriks, N.J.M. van den Nieuwelaar and F.W. Vaandrager. Model Checker Aided Design of a Controller for a Wafer Scanner. In International Journal on Software Tools for Technology Transfer (STTT) (6):633-647, Special Section on Quantitative Analysis of Real-time Embedded Systems, 2006. Also available as Technical Report NIII-R0430, NIII, University of Nijmegen, June 2004. Extended abstract in Proceedings 1st International Symposium on Leveraging Applications of Formal Methods (ISOLA'04), Cyprus, 30 October - 2 November 2004. This paper is referred to in patent application ASML ref. P-1784.010.


For a case-study of a wafer scanner from the semiconductor industry it is shown how model checking techniques can be used to compute (i) a simple yet optimal deadlock avoidance policy, and (ii) an infinite schedule that optimizes throughput. Deadlock avoidance is studied based on a simple finite state model using SMV, and for throughput analysis a more detailed timed automaton model has been constructed and analyzed using the UPPAAL tool. The SMV and UPPAAL models are formally related through the notion of a stuttering bisimulation. The results were obtained within two weeks, which confirms once more that model checking techniques may help to improve the design process of realistic, industrial systems. Methodologically, the case study is interesting since two models (and in fact also two model checkers) were used to obtain results that could not have been obtained using only a single model (tool).

DOI 10.1007/s10009-006-0025-7
Isola version PDF
Tech report PDF
Slides, SMV and UPPAAL models [Martijn Hendriks lecturing at ISOLA2004]